max c pld se ri es max cpld series altera s market-leading max® series of cplds are world-class low-cost devices designed for virtually any digital control function as non-volatile single-chip solutions max cplds are easy to incorporate into your system with the devices you can solve board-level issues such as insufficient i/o pins on a processor manage the power-up sequence or configuration of other more complex devices or inexpensively convert incompatible interfaces a.k.a glue logic designed to be hassle-free with intuitive device behavior and software max cplds give you the freedom to focus on your more complex design challenges max ii application areas · control signal distribution · led activity control · bus protocol translation · serial-to-parallel data conversion interface bridging i/o expansion key features · low cost · zero power · small packages · instant-on and non-volatile · in-system programmability isp · free quartus® ii web edition software support · free modelsim®-a
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cyc lonelow costf pg aseries cyclone fpga series maximum user i/o package/package size mm device t100 16 x 16 65 e/t1443 22 x 22 104 q208 30 x 30 q240 35 x 35 f256 17 x 17 u256 14 x 14 f324 19 x 19 249 f400 21 x 21 301 f484 23 x2 3 u484 19 x 19 f672 27 x 27 f780 29 x 29 f896 31 x 31 ep1c ep1c ep2c epc ep1c6 ep2c8/a epc10 ep1c12 ep2c1a epc16 ep1c20 ep2c20/a epc2 ep2c epc0 ep2c0 epc ep2c70 epc80 epc120 89 94 98 85 94 142 185 138 173 158 182 185 182 182 185 152 168 152 156 156 215 322 128 195 331 294 327 295 283 322 331 294 327 422 295 429 531 450 377 622 475 535 168 233 142 301 315 182 249 315 346 346 182 84 160 82 148 10 altera product catalog · 2007 · www.altera.com
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str at ix h ig h endf pga series stratix iii family features summary continued trimatrix memory trimatrix memory offers 3 memory block sizes to suit complex design needs 640-bit mlab blocks 9-kbit m9k blocks and 144-kbit m144k blocks with up to 21 mbits of memory performing at over 600 mhz and features such as dual-port ram and integrated error correction code ecc trimatrix memory is more flexible and efficient and provides higher memory bandwidth than any other memory architecture dsp blocks provide twice as many multiplier resources as competing architectures with up to 896 18-bit x 18-bit multipliers on the ep2se110 device dsp blocks include all associated pipelining adders and accumulators they are configurable to support 9-bit x 9-bit 12-bit x 12-bit 18-bit x 18-bit or 36-bit x 36-bit multipliers at up to 550 mhz stratix iii fpgas provide the industry s highest performance external dram and sram memory interfaces including ddr3 pvt compensated dedicated hard i/o structures with
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342 number indicates available user i/o pins vertical migration same vcc gnd isp and input pins user i/o may be less than labelled for vertical migration stratix ii fpgas 1.2 v high density high performance ep2sgx30d ep2sgx30c stratix ii gx fpgas 1.2 v 6.375-gbps transceivers ep2sgx130g ep2sgx60d ep2sgx60c ep2sgx60e ep2sgx90e ep2sgx90f all stratix series devices are offered in commercial and industrial temperatures and lead-free packages fbga f 8-pin flipchip 672-pin flipchip 780-pin 1,020-pin 1,12-pin 1,08-pin 342 366 342 500 334 492 534 718 758 902 308 534 742 742 534 1,126 1,170 558 650 734 361 361 364 364 hybrid fbga h 8-pin 345 number indicates available user i/o pins vertical migration same vcc gnd isp and input pins user i/o may be less than labelled for vertical migration stratix fpgas 1.5 v high density high performance ep1sgx10c stratix gx fpgas 1.5 v 3.1875-gbps transceivers ep1sgx10d ep1sgx25d ep1sgx40d ep1sgx40g ep1sgx25c ep1sgx25f ep1s10 ep1s20 ep1s25 ep1s30 ep1s40 ep1s
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need to move quickly from prototype to low-cost production altera s hardcopy structured asic series delivers unmatched product development flexibility and speed enabling you to make the most of your engineering resources and budget hardcopy structured asics are the market s only devices to offer a seamless prototype-to-production process for guaranteed success through its unique fpga front-end design flow the hardcopy series enables you to use altera s stratix series fpgas to develop verify and finalize your system design before you commit to silicon structured asics bridge the gap between standard cell asic technology and fpgas offering low unit costs combined with faster development times structured asics start with standard pre-tested base layers of logic and hard ip the proprietary design is then implemented on the top few metal layers within your existing design environment utilize stratix fpgas as your design s front end and then test it in-system when you re done altera s hardco
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nios ii embedded processors hardware development tools · quartus ii design software · sopc builder an exclusive quartus ii software tool that lets you processor cores the nios ii processor family consists of three cpu cores each optimized for a specific price and performance range all three cpu cores share a common 32-bit instruction set architecture are binary code compatible and are supported by the same software design suite simply choose which cpu is appropriate for each of your designs you can also create multi-core systems with any nios ii cpu to scale a system s performance or to break up software applications into simpler tasks build and evaluate systems at the block level easily and quickly · signaltap® ii embedded logic analyzer plug-in for the nios ii processor · fpgaview software from first silicon solutions for configuring and debugging altera fpga devices with tektronix logic analyzers nios ii processor family members feature description pipeline multiplier branch predict
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quartus ii design sof tware quartus ii design software quartus ii software subscription edition devices all web edition max and cyclone series arria gx family 95 download and dvd free license windows if you re looking for a design environment that will quickly move you from concept to creation choose altera s quartus ii design software number one in performance and productivity for cpld fpga and structured asic designs quartus ii software offers complete automated system definition and implementation all without requiring lower-level hdl or schematics this capability plus its seamless integration with leading eda software tools and flows will help turn your ideas into working systems in minutes features distribution cost operating system support 100 download and dvd paid license windows unix linux quartus ii design software features summary incremental compilation improves design timing closure and reduces design compilation times up to 70 percent supports team-based design enables pcb
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d eve lo pm e nt k i ts development kits continued product name and vendor name pci x/pci development kit pcixsys2 pldapplications dn7000k10pcis the dini group pci/pci-x board hitech global pci express design kit with stratix gx x1 x4 pldapplications 4-lane pci express kit hitech global device stratix ii ep2s60 to ep2s180 stratix ii ep2s90 ep2s130 or ep2s180 stratix ii ep2s90 and ep2s180 stratix gx ep1sgx40 features ideally suited for asic/fpga prototyping data acquisition applications complete logic element system providing asic or ip designers with a vehicle to cost effectively prototype logic and memory design pci/pci-x development platform includes free pci express ip core board license available for asic and fpga design flows endpoint root port and bridge and technical support four-lane low-cost pci express design kit eight-lane pci express pci and pci-x development platform pci/pci-x development platform stratix gx ep1sgx40 stratix gx ep1sgx40 stratix ep1s10f780 ep1s20f780 ep1s2
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online classes give you an overview of a variety of features and design techniques take advantage of these free online training modules to preview topics covered in greater depth in our instructor-led classes brush up on key how-to tips or even jump-start your design altera instructor-led training courses all courses are one day in length unless otherwise noted course category design languages software course titles · vhdl basics · verilog hdl basics · using quartus ii software an introduction · design planning guidelines for high-density fpgas · using quartus ii software schematic design · using quartus ii software timing analysis · using quartus ii software simulation · validating performance with the timequest static timing analyzer · switching to the timequest timing analyzer · constraining and analyzing timing for source synchronous circuits with timequest · introduction to incremental compilation · incremental compilation for team-based designs · using quartus ii software increme
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product websites and information · max cpld series max ii cplds www.altera.com/max2 max 3000a cplds www.altera.com/products/devices/max3k max 7000 cplds www.altera.com/products/devices/max7k · nios ii embedded processors nios ii processors www.altera.com/nios2 nios user forum www.niosforum.org nios ii development kits www.altera.com/nioskits nios ii c2h compiler www.altera.com/c2h · cyclone low-cost fpga series cyclone iii fpgas www.altera.com/cyclone3 cyclone ii fpgas www.altera.com/cyclone2 cyclone fpgas www.altera.com/cyclone have comments about this catalog email us at catalog@altera.com · intellectual property solutions ip megastore www.altera.com/ipmegastore · arria gx low-cost fpga family arria gx fpgas www.altera.com/arriagx · quartus ii design software quartus ii software www.altera.com/quartus2 quartus ii web edition and subscription edition download www.altera.com/download purchase quartus ii software www.altera.com/buysoftware quartus ii literature www.altera.com/literature
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